The MINC chip: Multistage Interconnection Network with Cache control mechanism chip

The Multistage Interconnection Network with Cache control mechanism (MINC) is a hardware mechanism to control the cache coherent in a switchconnected multiprocessors using a crossbar or Multistage Interconnection Network(MIN). In the MINC, the directory is located on the shared memory module, and the Reduced Hierarchical Bit-map Directory schemes(RHBDs) are used to reduce the directory. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. Using the 0.6 μm LPGA(Laser Programmable Gate Array) technology, the MINC chip(Network scale: 16input/16-output) is implemented in a single chip(26477 cells including 60Kbit memory). The chip works with at least 50MHz clock, and the total throughput of the chip is 800Mbyte/sec(50Mbyte/sec for each port).